A Configurable Floating-Point Discrete Hilbert Transform Processor for Accelerating the Calculation of Filter in Katsevich Formula

Katsevich formula is currently a hot topic for cone-beam computed tomography (CBCT). The filter in the formula can be computed by a regular discrete Hilbert transform (DHT). A configurable single precision floating-point (SPFP) DHT processor is proposed for accelerating the calculation of filter in Katsevich formula. The configurable processor is of memory based architecture with one pipelined butterfly processing engine (PE) and supports variable point sizes from 8 to 1024. The DHT processor is controlled by the address generator. According to the point size, the address generator yields one memory address pair per clock cycle to keep the processor accessing memories successively. The DHT is calculated easily via complex multiplications in the frequency domain. Two fast Fourier transforms (FFT) are required in the entire process. The radix-2 FFT algorithm with decimation-in-frequency (DIF) decomposition is utilized in the design to construct an efficiently signal flow graph (SFG) for DHT calculation. Arithmetic calculations, in the last FFT iteration, complex multiplications and the first IFFT iteration are replaced with conjugation and swapping operations, so two iterations are saved in the DHT SFG. Data are loaded and unloaded simultaneously after one frame data calculation is completed. The symmetric property of twiddle factors is utilized to decrease half size of the readonly memory (ROM). Truncation is used in the design to reduce data path width. The proposed DHT processor is written in Verilog HDL, so it is easy for ASIC implementation. Compared with previous works, the performance analysis shows that the proposed DHT processor has minimum clock latency. Key-Words: discrete Hilbert transform, FFT, floating-point adder, floating-point multiplier, ASIC, VLSI